The present technique relates to an apparatus and method for controlling rounding when performing a floating point operation.
There are various floating point operations that are typically expensive to perform accurately, in terms of the complexity of the circuitry required and/or the computation time required to produce the result. One such floating point operation is a floating point divide operation, where a first floating point number is divided by a second floating point number. To perform an accurate floating point divide operation typically takes a large number of clock cycles to perform, which can significantly impact the performance of the processing circuitry implementing the divide operation.
Whilst one may seek to construct dedicated logic circuitry to increase performance of such a divide operation, this would significantly increase the cost and complexity of the resulting processing circuitry, for example in terms of silicon area cost and high verification effort.
Typically techniques that seek to perform floating point division with less impact on performance cannot be guaranteed to produce entirely accurate results for the floating point divide operation.
It would be desirable to provide a mechanism that enabled certain floating point operations such as the above mentioned floating point divide operation to be performed more efficiently by data processing circuitry, whilst still ensuring that an accurate result is obtained.